CMOS PLL Synthesizers: Analysis and Design by Shu K., Sánchez-Sinencio E.

By Shu K., Sánchez-Sinencio E.

This booklet offers either basics and the cutting-edge of PLL synthesizer layout and research options. an entire assessment of either system-level and circuit-level layout and research are lined. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is applied in 0.35m m CMOS. It contains a high-speed and powerful phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which take on velocity and integration bottlenecks of PLL synthesizer elegantly.This e-book is conceived as a PLL synthesizer handbook for either academia researchers and layout engineers.

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749-753 J. Nieznanski, “An alternative approach to the ROM-less direct digital synthesis,” IEEE J. Solid-State Circuits, vol. 33, pp. 169-170, Jan. 1998 A. Yamagishi, M. Ishikawa, T. Tsuneo, and S. Date, “A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication,” IEEE J. Solid-State Circuits, vol. 33, pp. 210-217, Feb. 1998 A. Madisetti, A. Kwentus, and A. Willson, “A 100-MHz, 16-b, direct digital frequency synthesizer with 100-dBc spurious-free dynamic range,” IEEE J.

Miller and B. Conley, “A multiple modulator fractional divider,” Proc. , May 1990, pp. 559-568 [40] B. Miller and R. Conley, “A multiple modulator fractional divider,” IEEE Trans. Instrumentation and Measurement, vol. 40, pp. 578-583, June 1991 [41] T. Riley, M. Copeland, and T. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May 1993 [42] W. Yan and H. Luong, “A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers,” IEEE J.

Some dual-loop PLL frequency synthesizer architectures are shown in Fig. 2-11. In Fig. 2-11 (a), PLL1 is used to generate reference frequencies for PLL2. In Fig. 2-11 (b) PLL1 output is up-converted by PLL2 and a single-sideband (SSB) mixer. PLL1 generates tunable IF frequencies, while PLL2 generates a fixed RF frequency. In Fig. 2-11 (c) and (d), PLL2 and a SSB down-conversion mixer are used to reduce the divide ratio in PLL1. Recent works used the dual-loop PLL topology shown in Fig. 2-11 (e) for GSM receivers [42]-[44].

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