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Extra resources for An Introduction to Digital Techniques: Logic gates, Flip-flops, Counters and Shift registers
Toggle Fig. 50 Producing a squarewave from a signal with an uneven mark-space ratio. H_ L _1 HIE--two cycles~ Toggle input. Clock L Clock input. H-I L_ H. I I I Q U _,I I I Q ~] ~f one cycle I I )1 I Q output. L _ 51 Negative edge triggering Fig. 51 On page 47 positive edge triggering was described, and it was seen that once the FLIP-FLOP 'took up data', the data input could change to a new state. Some FLIPFLOPS take in data on the negative going edge of the clock pulse. These are called 'negative edge triggered' devices.
Fig. 45 The truth table. In a large number of applications, the outputs are required to change state with each clock pulse, as in the U704 circuit discussed on page 37. The change on each clock pulse may need to be delayed until required. This is the purpose of the T terminal on the toggle FLIPFLOP. CIRCUIT SYMBOL. 44. In this case there is a T input that controls the output. When the T input is 'low' then Q and 6 will remain unchanged, even if the FLIP-FLOP is clocked. When T is taken 'high', each time a clock pulse arrives the outputs will change state on the leading edge of the clock pulse.
As the positive going edges are equally spaced, each output half cycle will have the same duration, and so a square Naveform resuIts. When the toggle terminal is taken 'low' no change in output occurs. Fig. 49 Dividing a signal by the factor of 2. Toggle Fig. 50 Producing a squarewave from a signal with an uneven mark-space ratio. H_ L _1 HIE--two cycles~ Toggle input. Clock L Clock input. H-I L_ H. I I I Q U _,I I I Q ~] ~f one cycle I I )1 I Q output. L _ 51 Negative edge triggering Fig. 51 On page 47 positive edge triggering was described, and it was seen that once the FLIP-FLOP 'took up data', the data input could change to a new state.